Integrated circuit packaging conventionally has served to protect semiconductor dies, to provide electrical connections to the integrated circuitry on the dies, and to provide external terminals of a size and spacing suitable for systems or applications. However, integrated circuit device packaging has become increasingly complex as the size of semiconductor dies has decreased and the number of external terminals and the operating frequencies of integrated circuits have increased. As a result, improper or inefficient packaging can prevent an integrated circuit from reaching optimal operating performance.
Flip-chip packages with terminals in the form of a ball grid array (BGA) have been developed to eliminate bond wires and provide a large number of external terminals within a small package footprint. Flip-chip packages also require careful design for routing of power, ground, and signals for a high-speed or RF integrated circuit. For example, power and ground management techniques generally require relatively large traces or leads, which can make routing and shielding other signals in packages difficult to achieve within a limited package area. New packaging techniques and structures are desired that can improve package performance within a small package footprint.